An Implicit Multidimensional Parity based Data Coding and Decoding Algorithms with FPGA Implementation in Communication Systems

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An Implicit Multidimensional Parity based Data Coding and Decoding Algorithms with FPGA Implementation in Communication Systems

Mr. Vijay Santosh Tawar, Mr. Machchhindra Jibhau Garde

DOI : 10.46335/IJIES.2023.8.3.10

Abstract –The usability and use of devices in wireless communication is increasing gradually. The mobility and security of the system and the data integrity in the communication process are the requirements of the communication technology for the system. This is the main reason for the development of low voltage generators. Wireless communication medium consists of multiple signals, low voltage communication that can affect any system. Therefore, in wireless systems operating with low-power signals, it is best to use good data encoding and decoding strategies to send data over the medium.The data decoder can recognize changes in the data transmitted in the communication method and correct the data. This encoding-decoding process is calledDetection and Correction of error (EDAC) coding. One of such techniques, most often used in communication, is based on the concept of parity encoding and decoding. In the presented study, a multidimensional parity check based coding-decoding algorithm is proposed based on its results and simulation. With the help of proposed work, the associated process can be effectively used to detect and correct 3-bit errors in data transmission.