Performance Study of NOC Virtual Channel Router Architecture
Authors : Mr. Kamalkumar S. Kashyap Abstract—Thenetwork-on-chip (NOC) has been proposed for system-on–chip (SOC) based applications to achieve the better performance with low power consumption as compaired with typical on-chip bus architecture.Power consumption can be decreased by reducing the size of the router buffers. However, as reducing router buffers alone will significantly reduces performance, we […]
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