FPGA Based SDR For DPLL Application

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  • Create Date 29 July, 2025
  • Last Updated 30 July, 2025

Authors : Nikita Katole

AbstractTo design and developa system on chip reconfigurable modulesField Programmable Gate Array (FPGA) provides a way withhigh performance. In this paper, FPGA architectureis proposed, which would be a starting point for developingan efficient Software Defined Radio (SDR) architecture forrecovering audio signals from digitally modulated frequencywave. At themodulator and demodulator sections, a Digital FrequencyGenerator (DFG) is applied for generating the carrier wave byexploiting the quarter wave symmetry of sine or cosine waveswith dynamic range of more than 90dB.