Authors : Mr. Kamalkumar S. Kashyap
Abstract—Thenetwork-on-chip (NOC) has been proposed for system-on–chip (SOC) based applications to achieve the better performance with low power consumption as compaired with typical on-chip bus architecture.Power consumption can be decreased by reducing the size of the router buffers. However, as reducing router buffers alone will significantly reduces performance, we compensate by utilizing the newly proposed dual-function virtual channel buffers that allow flits to be stored on wires when required.This paper presents a novel virtual-channel (VC) sharing technique for NOC architecture. The proposed architecture improves the utilization of resources to enhance the performance with minimal overheads. Resource sharing for on-chip network is critical toreduce the chip area and power consumption. Thus virtual channel buffer sharing by other router ports has been proposed to enhance the performance of on-chip communication.
In this paper, we proposed the router architecture optimization by utilizing the ideal buffer instead of increasing number and size of buffers for desired area and power requirement results.
