Authors : Rajashree Talatule , Prof.K.S.Mankar
Abstract—Systolic arrays provide an alternative view of reconfigurable computing systems where real-time reconfiguration may be achieved by changing the sequence of events among the PEs forming the array. A rich selection of algorithms can be mapped into a systolic array structure .This paper is based on matrix multiplication using two methods i.e conventional and systolic architecture. . The simulation results have given that, the implementation of Systolic architecture requires less number of clock cycles then Conventional method.
